A technology that may reduce a size of mounted parts may include a system on chip (SoC) technology for fabricating a plurality of individual devices into one chip, and a system in package (SIP) technology for integrating a plurality of individual devices into a single package. These systems may be needed to reduce a weight and size of semiconductor devices.
SIP technology may be a technology for mounting a plurality of silicon chips horizontally and vertically into a single package. SIP technology may be an extension of a related art multi-chip module (MCM) concept. According to a related art MCM, horizontal mounting may be principally carried out at the time of fabricating a package. For SIP, on the other hand, a technology for vertically stacking a plurality of chips may be principally applied.
A related art technology for vertically stacking a plurality of chips may include a method for forming predetermined semiconductor devices on and/or over a first semiconductor substrate and a second semiconductor substrate, and bonding the first semiconductor substrate and the second semiconductor substrate using an adhesive.
Via holes may extend through a first semiconductor substrate and a second semiconductor substrate, and via electrodes may be formed in respective via holes. A first semiconductor substrate and a second semiconductor substrate may thus be electrically connected to each other.
A related art SIP technology may have various problems. For example, it may be difficult to bond a first semiconductor substrate and a second semiconductor substrate. In addition, it may be difficult to form via holes and via electrodes to electrically interconnect a first semiconductor substrate and a second semiconductor substrate due to a limit of a technology for grinding a back of a second semiconductor substrate.